1. Field of the Invention
The present invention relates to transceivers, and more particularly, to the testing of transceivers.
2. Description of Related Art
Many standards and protocols are now using a high-speed transceiver as part of their physical interface. The protocols cover a spectrum of applications including communications, computer, industrial and storage applications, where there is a need to move large quantities of data between chips or across backplanes, but where traditional parallel bus interfaces can no longer be relied upon.
Conventional techniques for testing a transceiver include utilizing a serial loopback. For instance, Ducaroir et al., U.S. Pat. No. 6,331,999, describes a test method utilizing a serial loopback, which is hereby incorporated by reference for all purposes. Although the serial loopback test is cost effective and can scale to match different transceiver data rates, it does not fully account for the jitter of the link. As such, a non-compliant link can still pass a standard serial loopback test. Even though there are other conventional techniques available for testing a transceiver, they utilize large and expensive test platforms.
Thus, there is a need for improved techniques and mechanisms that allow for an economical and scalable transceiver jitter test.